
binary-operation:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004006a8 <_init>:
  4006a8:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4006ac:	910003fd 	mov	x29, sp
  4006b0:	9400004e 	bl	4007e8 <call_weak_fn>
  4006b4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4006b8:	d65f03c0 	ret

Disassembly of section .plt:

00000000004006c0 <.plt>:
  4006c0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4006c4:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0xff48>
  4006c8:	f947fe11 	ldr	x17, [x16, #4088]
  4006cc:	913fe210 	add	x16, x16, #0xff8
  4006d0:	d61f0220 	br	x17
  4006d4:	d503201f 	nop
  4006d8:	d503201f 	nop
  4006dc:	d503201f 	nop

00000000004006e0 <exit@plt>:
  4006e0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006e4:	f9400211 	ldr	x17, [x16]
  4006e8:	91000210 	add	x16, x16, #0x0
  4006ec:	d61f0220 	br	x17

00000000004006f0 <perror@plt>:
  4006f0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006f4:	f9400611 	ldr	x17, [x16, #8]
  4006f8:	91002210 	add	x16, x16, #0x8
  4006fc:	d61f0220 	br	x17

0000000000400700 <atoi@plt>:
  400700:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400704:	f9400a11 	ldr	x17, [x16, #16]
  400708:	91004210 	add	x16, x16, #0x10
  40070c:	d61f0220 	br	x17

0000000000400710 <malloc@plt>:
  400710:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400714:	f9400e11 	ldr	x17, [x16, #24]
  400718:	91006210 	add	x16, x16, #0x18
  40071c:	d61f0220 	br	x17

0000000000400720 <__libc_start_main@plt>:
  400720:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400724:	f9401211 	ldr	x17, [x16, #32]
  400728:	91008210 	add	x16, x16, #0x20
  40072c:	d61f0220 	br	x17

0000000000400730 <__gmon_start__@plt>:
  400730:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400734:	f9401611 	ldr	x17, [x16, #40]
  400738:	9100a210 	add	x16, x16, #0x28
  40073c:	d61f0220 	br	x17

0000000000400740 <abort@plt>:
  400740:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400744:	f9401a11 	ldr	x17, [x16, #48]
  400748:	9100c210 	add	x16, x16, #0x30
  40074c:	d61f0220 	br	x17

0000000000400750 <free@plt>:
  400750:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400754:	f9401e11 	ldr	x17, [x16, #56]
  400758:	9100e210 	add	x16, x16, #0x38
  40075c:	d61f0220 	br	x17

0000000000400760 <__isoc99_scanf@plt>:
  400760:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400764:	f9402211 	ldr	x17, [x16, #64]
  400768:	91010210 	add	x16, x16, #0x40
  40076c:	d61f0220 	br	x17

0000000000400770 <printf@plt>:
  400770:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400774:	f9402611 	ldr	x17, [x16, #72]
  400778:	91012210 	add	x16, x16, #0x48
  40077c:	d61f0220 	br	x17

0000000000400780 <putchar@plt>:
  400780:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400784:	f9402a11 	ldr	x17, [x16, #80]
  400788:	91014210 	add	x16, x16, #0x50
  40078c:	d61f0220 	br	x17

0000000000400790 <fprintf@plt>:
  400790:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400794:	f9402e11 	ldr	x17, [x16, #88]
  400798:	91016210 	add	x16, x16, #0x58
  40079c:	d61f0220 	br	x17

Disassembly of section .text:

00000000004007a0 <_start>:
  4007a0:	d280001d 	mov	x29, #0x0                   	// #0
  4007a4:	d280001e 	mov	x30, #0x0                   	// #0
  4007a8:	aa0003e5 	mov	x5, x0
  4007ac:	f94003e1 	ldr	x1, [sp]
  4007b0:	910023e2 	add	x2, sp, #0x8
  4007b4:	910003e6 	mov	x6, sp
  4007b8:	580000c0 	ldr	x0, 4007d0 <_start+0x30>
  4007bc:	580000e3 	ldr	x3, 4007d8 <_start+0x38>
  4007c0:	58000104 	ldr	x4, 4007e0 <_start+0x40>
  4007c4:	97ffffd7 	bl	400720 <__libc_start_main@plt>
  4007c8:	97ffffde 	bl	400740 <abort@plt>
  4007cc:	00000000 	.inst	0x00000000 ; undefined
  4007d0:	00400d1c 	.word	0x00400d1c
  4007d4:	00000000 	.word	0x00000000
  4007d8:	00400f50 	.word	0x00400f50
  4007dc:	00000000 	.word	0x00000000
  4007e0:	00400fd0 	.word	0x00400fd0
  4007e4:	00000000 	.word	0x00000000

00000000004007e8 <call_weak_fn>:
  4007e8:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0xff48>
  4007ec:	f947f000 	ldr	x0, [x0, #4064]
  4007f0:	b4000040 	cbz	x0, 4007f8 <call_weak_fn+0x10>
  4007f4:	17ffffcf 	b	400730 <__gmon_start__@plt>
  4007f8:	d65f03c0 	ret
  4007fc:	00000000 	.inst	0x00000000 ; undefined

0000000000400800 <deregister_tm_clones>:
  400800:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400804:	9101c000 	add	x0, x0, #0x70
  400808:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  40080c:	9101c021 	add	x1, x1, #0x70
  400810:	eb00003f 	cmp	x1, x0
  400814:	540000a0 	b.eq	400828 <deregister_tm_clones+0x28>  // b.none
  400818:	90000001 	adrp	x1, 400000 <_init-0x6a8>
  40081c:	f947f821 	ldr	x1, [x1, #4080]
  400820:	b4000041 	cbz	x1, 400828 <deregister_tm_clones+0x28>
  400824:	d61f0020 	br	x1
  400828:	d65f03c0 	ret
  40082c:	d503201f 	nop

0000000000400830 <register_tm_clones>:
  400830:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400834:	9101c000 	add	x0, x0, #0x70
  400838:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  40083c:	9101c021 	add	x1, x1, #0x70
  400840:	cb000021 	sub	x1, x1, x0
  400844:	9343fc21 	asr	x1, x1, #3
  400848:	8b41fc21 	add	x1, x1, x1, lsr #63
  40084c:	9341fc21 	asr	x1, x1, #1
  400850:	b40000a1 	cbz	x1, 400864 <register_tm_clones+0x34>
  400854:	90000002 	adrp	x2, 400000 <_init-0x6a8>
  400858:	f947fc42 	ldr	x2, [x2, #4088]
  40085c:	b4000042 	cbz	x2, 400864 <register_tm_clones+0x34>
  400860:	d61f0040 	br	x2
  400864:	d65f03c0 	ret

0000000000400868 <__do_global_dtors_aux>:
  400868:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40086c:	910003fd 	mov	x29, sp
  400870:	f9000bf3 	str	x19, [sp, #16]
  400874:	d0000093 	adrp	x19, 412000 <exit@GLIBC_2.17>
  400878:	3941e260 	ldrb	w0, [x19, #120]
  40087c:	35000080 	cbnz	w0, 40088c <__do_global_dtors_aux+0x24>
  400880:	97ffffe0 	bl	400800 <deregister_tm_clones>
  400884:	52800020 	mov	w0, #0x1                   	// #1
  400888:	3901e260 	strb	w0, [x19, #120]
  40088c:	f9400bf3 	ldr	x19, [sp, #16]
  400890:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400894:	d65f03c0 	ret

0000000000400898 <frame_dummy>:
  400898:	17ffffe6 	b	400830 <register_tm_clones>

000000000040089c <search_for_insert>:
  40089c:	d10083ff 	sub	sp, sp, #0x20
  4008a0:	f90007e0 	str	x0, [sp, #8]
  4008a4:	b90007e1 	str	w1, [sp, #4]
  4008a8:	f94007e0 	ldr	x0, [sp, #8]
  4008ac:	f9400000 	ldr	x0, [x0]
  4008b0:	f9000be0 	str	x0, [sp, #16]
  4008b4:	14000015 	b	400908 <search_for_insert+0x6c>
  4008b8:	f9400be0 	ldr	x0, [sp, #16]
  4008bc:	f9000fe0 	str	x0, [sp, #24]
  4008c0:	f9400be0 	ldr	x0, [sp, #16]
  4008c4:	b9400000 	ldr	w0, [x0]
  4008c8:	b94007e1 	ldr	w1, [sp, #4]
  4008cc:	6b00003f 	cmp	w1, w0
  4008d0:	54000061 	b.ne	4008dc <search_for_insert+0x40>  // b.any
  4008d4:	d2800000 	mov	x0, #0x0                   	// #0
  4008d8:	14000010 	b	400918 <search_for_insert+0x7c>
  4008dc:	f9400be0 	ldr	x0, [sp, #16]
  4008e0:	b9400000 	ldr	w0, [x0]
  4008e4:	b94007e1 	ldr	w1, [sp, #4]
  4008e8:	6b00003f 	cmp	w1, w0
  4008ec:	5400008a 	b.ge	4008fc <search_for_insert+0x60>  // b.tcont
  4008f0:	f9400be0 	ldr	x0, [sp, #16]
  4008f4:	f9400400 	ldr	x0, [x0, #8]
  4008f8:	14000003 	b	400904 <search_for_insert+0x68>
  4008fc:	f9400be0 	ldr	x0, [sp, #16]
  400900:	f9400800 	ldr	x0, [x0, #16]
  400904:	f9000be0 	str	x0, [sp, #16]
  400908:	f9400be0 	ldr	x0, [sp, #16]
  40090c:	f100001f 	cmp	x0, #0x0
  400910:	54fffd41 	b.ne	4008b8 <search_for_insert+0x1c>  // b.any
  400914:	f9400fe0 	ldr	x0, [sp, #24]
  400918:	910083ff 	add	sp, sp, #0x20
  40091c:	d65f03c0 	ret

0000000000400920 <insert>:
  400920:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400924:	910003fd 	mov	x29, sp
  400928:	f9000fa0 	str	x0, [x29, #24]
  40092c:	b90017a1 	str	w1, [x29, #20]
  400930:	d2800300 	mov	x0, #0x18                  	// #24
  400934:	97ffff77 	bl	400710 <malloc@plt>
  400938:	f90017a0 	str	x0, [x29, #40]
  40093c:	f94017a0 	ldr	x0, [x29, #40]
  400940:	f100001f 	cmp	x0, #0x0
  400944:	54000081 	b.ne	400954 <insert+0x34>  // b.any
  400948:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x18>
  40094c:	91000000 	add	x0, x0, #0x0
  400950:	97ffff68 	bl	4006f0 <perror@plt>
  400954:	f94017a0 	ldr	x0, [x29, #40]
  400958:	b94017a1 	ldr	w1, [x29, #20]
  40095c:	b9000001 	str	w1, [x0]
  400960:	f94017a0 	ldr	x0, [x29, #40]
  400964:	f900041f 	str	xzr, [x0, #8]
  400968:	f94017a0 	ldr	x0, [x29, #40]
  40096c:	f900081f 	str	xzr, [x0, #16]
  400970:	f9400fa0 	ldr	x0, [x29, #24]
  400974:	f9400000 	ldr	x0, [x0]
  400978:	f100001f 	cmp	x0, #0x0
  40097c:	540000a1 	b.ne	400990 <insert+0x70>  // b.any
  400980:	f9400fa0 	ldr	x0, [x29, #24]
  400984:	f94017a1 	ldr	x1, [x29, #40]
  400988:	f9000001 	str	x1, [x0]
  40098c:	14000020 	b	400a0c <insert+0xec>
  400990:	b94017a1 	ldr	w1, [x29, #20]
  400994:	f9400fa0 	ldr	x0, [x29, #24]
  400998:	97ffffc1 	bl	40089c <search_for_insert>
  40099c:	f90013a0 	str	x0, [x29, #32]
  4009a0:	f94013a0 	ldr	x0, [x29, #32]
  4009a4:	f100001f 	cmp	x0, #0x0
  4009a8:	540001a1 	b.ne	4009dc <insert+0xbc>  // b.any
  4009ac:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4009b0:	9101c000 	add	x0, x0, #0x70
  4009b4:	f9400003 	ldr	x3, [x0]
  4009b8:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x18>
  4009bc:	91008000 	add	x0, x0, #0x20
  4009c0:	b94017a2 	ldr	w2, [x29, #20]
  4009c4:	aa0003e1 	mov	x1, x0
  4009c8:	aa0303e0 	mov	x0, x3
  4009cc:	97ffff71 	bl	400790 <fprintf@plt>
  4009d0:	f94017a0 	ldr	x0, [x29, #40]
  4009d4:	97ffff5f 	bl	400750 <free@plt>
  4009d8:	1400000d 	b	400a0c <insert+0xec>
  4009dc:	f94013a0 	ldr	x0, [x29, #32]
  4009e0:	b9400000 	ldr	w0, [x0]
  4009e4:	b94017a1 	ldr	w1, [x29, #20]
  4009e8:	6b00003f 	cmp	w1, w0
  4009ec:	540000aa 	b.ge	400a00 <insert+0xe0>  // b.tcont
  4009f0:	f94013a0 	ldr	x0, [x29, #32]
  4009f4:	f94017a1 	ldr	x1, [x29, #40]
  4009f8:	f9000401 	str	x1, [x0, #8]
  4009fc:	14000004 	b	400a0c <insert+0xec>
  400a00:	f94013a0 	ldr	x0, [x29, #32]
  400a04:	f94017a1 	ldr	x1, [x29, #40]
  400a08:	f9000801 	str	x1, [x0, #16]
  400a0c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400a10:	d65f03c0 	ret

0000000000400a14 <print>:
  400a14:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400a18:	910003fd 	mov	x29, sp
  400a1c:	b9001fa0 	str	w0, [x29, #28]
  400a20:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x18>
  400a24:	9100e000 	add	x0, x0, #0x38
  400a28:	b9401fa1 	ldr	w1, [x29, #28]
  400a2c:	97ffff51 	bl	400770 <printf@plt>
  400a30:	52800020 	mov	w0, #0x1                   	// #1
  400a34:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400a38:	d65f03c0 	ret

0000000000400a3c <preorder>:
  400a3c:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400a40:	910003fd 	mov	x29, sp
  400a44:	f9000fa0 	str	x0, [x29, #24]
  400a48:	f9000ba1 	str	x1, [x29, #16]
  400a4c:	f9400fa0 	ldr	x0, [x29, #24]
  400a50:	f100001f 	cmp	x0, #0x0
  400a54:	540002e0 	b.eq	400ab0 <preorder+0x74>  // b.none
  400a58:	f9400fa0 	ldr	x0, [x29, #24]
  400a5c:	b9400000 	ldr	w0, [x0]
  400a60:	f9400ba1 	ldr	x1, [x29, #16]
  400a64:	d63f0020 	blr	x1
  400a68:	7100001f 	cmp	w0, #0x0
  400a6c:	540001e0 	b.eq	400aa8 <preorder+0x6c>  // b.none
  400a70:	f9400fa0 	ldr	x0, [x29, #24]
  400a74:	f9400400 	ldr	x0, [x0, #8]
  400a78:	f9400ba1 	ldr	x1, [x29, #16]
  400a7c:	97fffff0 	bl	400a3c <preorder>
  400a80:	7100001f 	cmp	w0, #0x0
  400a84:	54000120 	b.eq	400aa8 <preorder+0x6c>  // b.none
  400a88:	f9400fa0 	ldr	x0, [x29, #24]
  400a8c:	f9400800 	ldr	x0, [x0, #16]
  400a90:	f9400ba1 	ldr	x1, [x29, #16]
  400a94:	97ffffea 	bl	400a3c <preorder>
  400a98:	7100001f 	cmp	w0, #0x0
  400a9c:	54000060 	b.eq	400aa8 <preorder+0x6c>  // b.none
  400aa0:	52800020 	mov	w0, #0x1                   	// #1
  400aa4:	14000004 	b	400ab4 <preorder+0x78>
  400aa8:	52800000 	mov	w0, #0x0                   	// #0
  400aac:	14000002 	b	400ab4 <preorder+0x78>
  400ab0:	52800020 	mov	w0, #0x1                   	// #1
  400ab4:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400ab8:	d65f03c0 	ret

0000000000400abc <inorder>:
  400abc:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400ac0:	910003fd 	mov	x29, sp
  400ac4:	f9000fa0 	str	x0, [x29, #24]
  400ac8:	f9000ba1 	str	x1, [x29, #16]
  400acc:	f9400fa0 	ldr	x0, [x29, #24]
  400ad0:	f100001f 	cmp	x0, #0x0
  400ad4:	540002e0 	b.eq	400b30 <inorder+0x74>  // b.none
  400ad8:	f9400fa0 	ldr	x0, [x29, #24]
  400adc:	f9400400 	ldr	x0, [x0, #8]
  400ae0:	f9400ba1 	ldr	x1, [x29, #16]
  400ae4:	97fffff6 	bl	400abc <inorder>
  400ae8:	7100001f 	cmp	w0, #0x0
  400aec:	540001e0 	b.eq	400b28 <inorder+0x6c>  // b.none
  400af0:	f9400fa0 	ldr	x0, [x29, #24]
  400af4:	b9400000 	ldr	w0, [x0]
  400af8:	f9400ba1 	ldr	x1, [x29, #16]
  400afc:	d63f0020 	blr	x1
  400b00:	7100001f 	cmp	w0, #0x0
  400b04:	54000120 	b.eq	400b28 <inorder+0x6c>  // b.none
  400b08:	f9400fa0 	ldr	x0, [x29, #24]
  400b0c:	f9400800 	ldr	x0, [x0, #16]
  400b10:	f9400ba1 	ldr	x1, [x29, #16]
  400b14:	97ffffea 	bl	400abc <inorder>
  400b18:	7100001f 	cmp	w0, #0x0
  400b1c:	54000060 	b.eq	400b28 <inorder+0x6c>  // b.none
  400b20:	52800020 	mov	w0, #0x1                   	// #1
  400b24:	14000004 	b	400b34 <inorder+0x78>
  400b28:	52800000 	mov	w0, #0x0                   	// #0
  400b2c:	14000002 	b	400b34 <inorder+0x78>
  400b30:	52800020 	mov	w0, #0x1                   	// #1
  400b34:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400b38:	d65f03c0 	ret

0000000000400b3c <delete>:
  400b3c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400b40:	910003fd 	mov	x29, sp
  400b44:	f9000fa0 	str	x0, [x29, #24]
  400b48:	b90017a1 	str	w1, [x29, #20]
  400b4c:	f9400fa0 	ldr	x0, [x29, #24]
  400b50:	f9400000 	ldr	x0, [x0]
  400b54:	f90017a0 	str	x0, [x29, #40]
  400b58:	f94017a0 	ldr	x0, [x29, #40]
  400b5c:	f100001f 	cmp	x0, #0x0
  400b60:	54000161 	b.ne	400b8c <delete+0x50>  // b.any
  400b64:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400b68:	9101c000 	add	x0, x0, #0x70
  400b6c:	f9400003 	ldr	x3, [x0]
  400b70:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x18>
  400b74:	91010000 	add	x0, x0, #0x40
  400b78:	b94017a2 	ldr	w2, [x29, #20]
  400b7c:	aa0003e1 	mov	x1, x0
  400b80:	aa0303e0 	mov	x0, x3
  400b84:	97ffff03 	bl	400790 <fprintf@plt>
  400b88:	14000063 	b	400d14 <delete+0x1d8>
  400b8c:	f94017a0 	ldr	x0, [x29, #40]
  400b90:	b9400000 	ldr	w0, [x0]
  400b94:	b94017a1 	ldr	w1, [x29, #20]
  400b98:	6b00003f 	cmp	w1, w0
  400b9c:	54000961 	b.ne	400cc8 <delete+0x18c>  // b.any
  400ba0:	f94017a0 	ldr	x0, [x29, #40]
  400ba4:	f9400800 	ldr	x0, [x0, #16]
  400ba8:	f100001f 	cmp	x0, #0x0
  400bac:	54000141 	b.ne	400bd4 <delete+0x98>  // b.any
  400bb0:	f94017a0 	ldr	x0, [x29, #40]
  400bb4:	f9400400 	ldr	x0, [x0, #8]
  400bb8:	f100001f 	cmp	x0, #0x0
  400bbc:	540000c1 	b.ne	400bd4 <delete+0x98>  // b.any
  400bc0:	f9400fa0 	ldr	x0, [x29, #24]
  400bc4:	f900001f 	str	xzr, [x0]
  400bc8:	f94017a0 	ldr	x0, [x29, #40]
  400bcc:	97fffee1 	bl	400750 <free@plt>
  400bd0:	14000051 	b	400d14 <delete+0x1d8>
  400bd4:	f94017a0 	ldr	x0, [x29, #40]
  400bd8:	f9400800 	ldr	x0, [x0, #16]
  400bdc:	f100001f 	cmp	x0, #0x0
  400be0:	54000101 	b.ne	400c00 <delete+0xc4>  // b.any
  400be4:	f94017a0 	ldr	x0, [x29, #40]
  400be8:	f9400401 	ldr	x1, [x0, #8]
  400bec:	f9400fa0 	ldr	x0, [x29, #24]
  400bf0:	f9000001 	str	x1, [x0]
  400bf4:	f94017a0 	ldr	x0, [x29, #40]
  400bf8:	97fffed6 	bl	400750 <free@plt>
  400bfc:	14000046 	b	400d14 <delete+0x1d8>
  400c00:	f94017a0 	ldr	x0, [x29, #40]
  400c04:	f9400400 	ldr	x0, [x0, #8]
  400c08:	f100001f 	cmp	x0, #0x0
  400c0c:	54000101 	b.ne	400c2c <delete+0xf0>  // b.any
  400c10:	f94017a0 	ldr	x0, [x29, #40]
  400c14:	f9400801 	ldr	x1, [x0, #16]
  400c18:	f9400fa0 	ldr	x0, [x29, #24]
  400c1c:	f9000001 	str	x1, [x0]
  400c20:	f94017a0 	ldr	x0, [x29, #40]
  400c24:	97fffecb 	bl	400750 <free@plt>
  400c28:	1400003b 	b	400d14 <delete+0x1d8>
  400c2c:	f94017a0 	ldr	x0, [x29, #40]
  400c30:	f9400800 	ldr	x0, [x0, #16]
  400c34:	f9001ba0 	str	x0, [x29, #48]
  400c38:	f9401ba0 	ldr	x0, [x29, #48]
  400c3c:	f9400400 	ldr	x0, [x0, #8]
  400c40:	f100001f 	cmp	x0, #0x0
  400c44:	54000161 	b.ne	400c70 <delete+0x134>  // b.any
  400c48:	f94017a0 	ldr	x0, [x29, #40]
  400c4c:	f9400401 	ldr	x1, [x0, #8]
  400c50:	f9401ba0 	ldr	x0, [x29, #48]
  400c54:	f9000401 	str	x1, [x0, #8]
  400c58:	14000016 	b	400cb0 <delete+0x174>
  400c5c:	f9401ba0 	ldr	x0, [x29, #48]
  400c60:	f9001fa0 	str	x0, [x29, #56]
  400c64:	f9401ba0 	ldr	x0, [x29, #48]
  400c68:	f9400400 	ldr	x0, [x0, #8]
  400c6c:	f9001ba0 	str	x0, [x29, #48]
  400c70:	f9401ba0 	ldr	x0, [x29, #48]
  400c74:	f9400400 	ldr	x0, [x0, #8]
  400c78:	f100001f 	cmp	x0, #0x0
  400c7c:	54ffff01 	b.ne	400c5c <delete+0x120>  // b.any
  400c80:	f9401ba0 	ldr	x0, [x29, #48]
  400c84:	f9400801 	ldr	x1, [x0, #16]
  400c88:	f9401fa0 	ldr	x0, [x29, #56]
  400c8c:	f9000401 	str	x1, [x0, #8]
  400c90:	f94017a0 	ldr	x0, [x29, #40]
  400c94:	f9400401 	ldr	x1, [x0, #8]
  400c98:	f9401ba0 	ldr	x0, [x29, #48]
  400c9c:	f9000401 	str	x1, [x0, #8]
  400ca0:	f94017a0 	ldr	x0, [x29, #40]
  400ca4:	f9400801 	ldr	x1, [x0, #16]
  400ca8:	f9401ba0 	ldr	x0, [x29, #48]
  400cac:	f9000801 	str	x1, [x0, #16]
  400cb0:	f9400fa0 	ldr	x0, [x29, #24]
  400cb4:	f9401ba1 	ldr	x1, [x29, #48]
  400cb8:	f9000001 	str	x1, [x0]
  400cbc:	f94017a0 	ldr	x0, [x29, #40]
  400cc0:	97fffea4 	bl	400750 <free@plt>
  400cc4:	14000014 	b	400d14 <delete+0x1d8>
  400cc8:	f94017a0 	ldr	x0, [x29, #40]
  400ccc:	b9400000 	ldr	w0, [x0]
  400cd0:	b94017a1 	ldr	w1, [x29, #20]
  400cd4:	6b00003f 	cmp	w1, w0
  400cd8:	540000cd 	b.le	400cf0 <delete+0x1b4>
  400cdc:	f94017a0 	ldr	x0, [x29, #40]
  400ce0:	91004000 	add	x0, x0, #0x10
  400ce4:	b94017a1 	ldr	w1, [x29, #20]
  400ce8:	97ffff95 	bl	400b3c <delete>
  400cec:	1400000a 	b	400d14 <delete+0x1d8>
  400cf0:	f94017a0 	ldr	x0, [x29, #40]
  400cf4:	b9400000 	ldr	w0, [x0]
  400cf8:	b94017a1 	ldr	w1, [x29, #20]
  400cfc:	6b00003f 	cmp	w1, w0
  400d00:	540000aa 	b.ge	400d14 <delete+0x1d8>  // b.tcont
  400d04:	f94017a0 	ldr	x0, [x29, #40]
  400d08:	91002000 	add	x0, x0, #0x8
  400d0c:	b94017a1 	ldr	w1, [x29, #20]
  400d10:	97ffff8b 	bl	400b3c <delete>
  400d14:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400d18:	d65f03c0 	ret

0000000000400d1c <main>:
  400d1c:	a9b77bfd 	stp	x29, x30, [sp, #-144]!
  400d20:	910003fd 	mov	x29, sp
  400d24:	a90153f3 	stp	x19, x20, [sp, #16]
  400d28:	a9025bf5 	stp	x21, x22, [sp, #32]
  400d2c:	a90363f7 	stp	x23, x24, [sp, #48]
  400d30:	a9046bf9 	stp	x25, x26, [sp, #64]
  400d34:	f9002bfb 	str	x27, [sp, #80]
  400d38:	b9006fa0 	str	w0, [x29, #108]
  400d3c:	f90033a1 	str	x1, [x29, #96]
  400d40:	910003e0 	mov	x0, sp
  400d44:	aa0003fb 	mov	x27, x0
  400d48:	f9003bbf 	str	xzr, [x29, #112]
  400d4c:	b9406fa0 	ldr	w0, [x29, #108]
  400d50:	7100041f 	cmp	w0, #0x1
  400d54:	540001cc 	b.gt	400d8c <main+0x70>
  400d58:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400d5c:	9101c000 	add	x0, x0, #0x70
  400d60:	f9400003 	ldr	x3, [x0]
  400d64:	f94033a0 	ldr	x0, [x29, #96]
  400d68:	f9400001 	ldr	x1, [x0]
  400d6c:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x18>
  400d70:	91014000 	add	x0, x0, #0x50
  400d74:	aa0103e2 	mov	x2, x1
  400d78:	aa0003e1 	mov	x1, x0
  400d7c:	aa0303e0 	mov	x0, x3
  400d80:	97fffe84 	bl	400790 <fprintf@plt>
  400d84:	12800000 	mov	w0, #0xffffffff            	// #-1
  400d88:	97fffe56 	bl	4006e0 <exit@plt>
  400d8c:	f94033a0 	ldr	x0, [x29, #96]
  400d90:	91002000 	add	x0, x0, #0x8
  400d94:	f9400000 	ldr	x0, [x0]
  400d98:	97fffe5a 	bl	400700 <atoi@plt>
  400d9c:	b9008ba0 	str	w0, [x29, #136]
  400da0:	b9408ba0 	ldr	w0, [x29, #136]
  400da4:	93407c01 	sxtw	x1, w0
  400da8:	d1000421 	sub	x1, x1, #0x1
  400dac:	f90043a1 	str	x1, [x29, #128]
  400db0:	93407c01 	sxtw	x1, w0
  400db4:	aa0103f9 	mov	x25, x1
  400db8:	d280001a 	mov	x26, #0x0                   	// #0
  400dbc:	d37bff21 	lsr	x1, x25, #59
  400dc0:	d37beb56 	lsl	x22, x26, #5
  400dc4:	aa160036 	orr	x22, x1, x22
  400dc8:	d37beb35 	lsl	x21, x25, #5
  400dcc:	93407c01 	sxtw	x1, w0
  400dd0:	aa0103f7 	mov	x23, x1
  400dd4:	d2800018 	mov	x24, #0x0                   	// #0
  400dd8:	d37bfee1 	lsr	x1, x23, #59
  400ddc:	d37beb14 	lsl	x20, x24, #5
  400de0:	aa140034 	orr	x20, x1, x20
  400de4:	d37beaf3 	lsl	x19, x23, #5
  400de8:	93407c00 	sxtw	x0, w0
  400dec:	d37ef400 	lsl	x0, x0, #2
  400df0:	91000c00 	add	x0, x0, #0x3
  400df4:	91003c00 	add	x0, x0, #0xf
  400df8:	d344fc00 	lsr	x0, x0, #4
  400dfc:	d37cec00 	lsl	x0, x0, #4
  400e00:	cb2063ff 	sub	sp, sp, x0
  400e04:	910003e0 	mov	x0, sp
  400e08:	91000c00 	add	x0, x0, #0x3
  400e0c:	d342fc00 	lsr	x0, x0, #2
  400e10:	d37ef400 	lsl	x0, x0, #2
  400e14:	f9003fa0 	str	x0, [x29, #120]
  400e18:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x18>
  400e1c:	91018000 	add	x0, x0, #0x60
  400e20:	b9408ba1 	ldr	w1, [x29, #136]
  400e24:	97fffe53 	bl	400770 <printf@plt>
  400e28:	b9008fbf 	str	wzr, [x29, #140]
  400e2c:	14000010 	b	400e6c <main+0x150>
  400e30:	b9808fa0 	ldrsw	x0, [x29, #140]
  400e34:	d37ef400 	lsl	x0, x0, #2
  400e38:	f9403fa1 	ldr	x1, [x29, #120]
  400e3c:	8b000021 	add	x1, x1, x0
  400e40:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x18>
  400e44:	91020000 	add	x0, x0, #0x80
  400e48:	97fffe46 	bl	400760 <__isoc99_scanf@plt>
  400e4c:	f9403fa0 	ldr	x0, [x29, #120]
  400e50:	b9808fa1 	ldrsw	x1, [x29, #140]
  400e54:	b8617801 	ldr	w1, [x0, x1, lsl #2]
  400e58:	9101c3a0 	add	x0, x29, #0x70
  400e5c:	97fffeb1 	bl	400920 <insert>
  400e60:	b9408fa0 	ldr	w0, [x29, #140]
  400e64:	11000400 	add	w0, w0, #0x1
  400e68:	b9008fa0 	str	w0, [x29, #140]
  400e6c:	b9408fa1 	ldr	w1, [x29, #140]
  400e70:	b9408ba0 	ldr	w0, [x29, #136]
  400e74:	6b00003f 	cmp	w1, w0
  400e78:	54fffdcb 	b.lt	400e30 <main+0x114>  // b.tstop
  400e7c:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x18>
  400e80:	91022000 	add	x0, x0, #0x88
  400e84:	97fffe3b 	bl	400770 <printf@plt>
  400e88:	f9403ba2 	ldr	x2, [x29, #112]
  400e8c:	90000000 	adrp	x0, 400000 <_init-0x6a8>
  400e90:	91285000 	add	x0, x0, #0xa14
  400e94:	aa0003e1 	mov	x1, x0
  400e98:	aa0203e0 	mov	x0, x2
  400e9c:	97fffee8 	bl	400a3c <preorder>
  400ea0:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x18>
  400ea4:	91028000 	add	x0, x0, #0xa0
  400ea8:	97fffe32 	bl	400770 <printf@plt>
  400eac:	f9403ba2 	ldr	x2, [x29, #112]
  400eb0:	90000000 	adrp	x0, 400000 <_init-0x6a8>
  400eb4:	91285000 	add	x0, x0, #0xa14
  400eb8:	aa0003e1 	mov	x1, x0
  400ebc:	aa0203e0 	mov	x0, x2
  400ec0:	97fffeff 	bl	400abc <inorder>
  400ec4:	52800140 	mov	w0, #0xa                   	// #10
  400ec8:	97fffe2e 	bl	400780 <putchar@plt>
  400ecc:	9101c3a0 	add	x0, x29, #0x70
  400ed0:	528005a1 	mov	w1, #0x2d                  	// #45
  400ed4:	97ffff1a 	bl	400b3c <delete>
  400ed8:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x18>
  400edc:	91022000 	add	x0, x0, #0x88
  400ee0:	97fffe24 	bl	400770 <printf@plt>
  400ee4:	f9403ba2 	ldr	x2, [x29, #112]
  400ee8:	90000000 	adrp	x0, 400000 <_init-0x6a8>
  400eec:	91285000 	add	x0, x0, #0xa14
  400ef0:	aa0003e1 	mov	x1, x0
  400ef4:	aa0203e0 	mov	x0, x2
  400ef8:	97fffed1 	bl	400a3c <preorder>
  400efc:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x18>
  400f00:	91028000 	add	x0, x0, #0xa0
  400f04:	97fffe1b 	bl	400770 <printf@plt>
  400f08:	f9403ba2 	ldr	x2, [x29, #112]
  400f0c:	90000000 	adrp	x0, 400000 <_init-0x6a8>
  400f10:	91285000 	add	x0, x0, #0xa14
  400f14:	aa0003e1 	mov	x1, x0
  400f18:	aa0203e0 	mov	x0, x2
  400f1c:	97fffee8 	bl	400abc <inorder>
  400f20:	52800140 	mov	w0, #0xa                   	// #10
  400f24:	97fffe17 	bl	400780 <putchar@plt>
  400f28:	9100037f 	mov	sp, x27
  400f2c:	52800000 	mov	w0, #0x0                   	// #0
  400f30:	910003bf 	mov	sp, x29
  400f34:	a94153f3 	ldp	x19, x20, [sp, #16]
  400f38:	a9425bf5 	ldp	x21, x22, [sp, #32]
  400f3c:	a94363f7 	ldp	x23, x24, [sp, #48]
  400f40:	a9446bf9 	ldp	x25, x26, [sp, #64]
  400f44:	f9402bfb 	ldr	x27, [sp, #80]
  400f48:	a8c97bfd 	ldp	x29, x30, [sp], #144
  400f4c:	d65f03c0 	ret

0000000000400f50 <__libc_csu_init>:
  400f50:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400f54:	910003fd 	mov	x29, sp
  400f58:	a901d7f4 	stp	x20, x21, [sp, #24]
  400f5c:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0xff48>
  400f60:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0xff48>
  400f64:	91374294 	add	x20, x20, #0xdd0
  400f68:	913722b5 	add	x21, x21, #0xdc8
  400f6c:	a902dff6 	stp	x22, x23, [sp, #40]
  400f70:	cb150294 	sub	x20, x20, x21
  400f74:	f9001ff8 	str	x24, [sp, #56]
  400f78:	2a0003f6 	mov	w22, w0
  400f7c:	aa0103f7 	mov	x23, x1
  400f80:	9343fe94 	asr	x20, x20, #3
  400f84:	aa0203f8 	mov	x24, x2
  400f88:	97fffdc8 	bl	4006a8 <_init>
  400f8c:	b4000194 	cbz	x20, 400fbc <__libc_csu_init+0x6c>
  400f90:	f9000bb3 	str	x19, [x29, #16]
  400f94:	d2800013 	mov	x19, #0x0                   	// #0
  400f98:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400f9c:	aa1803e2 	mov	x2, x24
  400fa0:	aa1703e1 	mov	x1, x23
  400fa4:	2a1603e0 	mov	w0, w22
  400fa8:	91000673 	add	x19, x19, #0x1
  400fac:	d63f0060 	blr	x3
  400fb0:	eb13029f 	cmp	x20, x19
  400fb4:	54ffff21 	b.ne	400f98 <__libc_csu_init+0x48>  // b.any
  400fb8:	f9400bb3 	ldr	x19, [x29, #16]
  400fbc:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400fc0:	a942dff6 	ldp	x22, x23, [sp, #40]
  400fc4:	f9401ff8 	ldr	x24, [sp, #56]
  400fc8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400fcc:	d65f03c0 	ret

0000000000400fd0 <__libc_csu_fini>:
  400fd0:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400fd4 <_fini>:
  400fd4:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400fd8:	910003fd 	mov	x29, sp
  400fdc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400fe0:	d65f03c0 	ret
